CSA Computer System Architecture by Morris Mano, Ch 8 Answers:
8-1. a. 32 MUX of size 16X1 each.
b. 4 and 4
c. 4 and 16
d. 32+32+32=96
e. 4(SELA)+4(SELB)+4(SELD)+6(OPR)= 18 bit word is required.
8-2. 30+80+10=120ns.
8-3. a. 010 011 001 00010
b. 100 000 100 00000
c. 101 000 101 00101
d. 001 000 110 11000
e. 000 000 111 00001
8-4. a. R3<-R1-R2 (SUB)
b. OUTPUT<-INPUT (TRFA)
c. R2<-0 (XOR)
d. OUTPUT<-INPUT+R1 (ADD)
e. R3<-shr(R7) (SHRA)
8-5. a. 2^6=64
b. 0
8-6. PUSH:
M[SP]<-DR
SP<-SP-1
POP:
SP<-SP+1
DR<-M[SP]
(also range of SP has to be checked in both the above cases)
8-7. a. AB*CD*+EF*
b. BD*CE*+A*AB*+
c. FG+E*CD*+B*A+
d. DE+C*B+A*GH+F*/
8-8. a. A/(B-C*(D+E))
b. (D*E/C)-B+A
c. (A/B*C)-D+(E/F)
d. (((F+G)*E+D)*C+B)*A
8-9.Expression in Postfix Notion:
3 4 + 8 10 2 6 + * + *
Following are the Stack iterations and stack increases from left to right:
1. 3
2. 3 4
3. 7
4. 7 8
5. 7 8 10
6. 7 8 10 2
7. 7 8 10 2 6
8. 7 8 10 8
9. 7 8 80
10. 7 88
11. 616=Answer
8-10.
8-11. 6 * (2^12)
8-12. a.
MUL R1 D E
SUB R1 R1 F
MUL R1 C R1
ADD R1 B R1
SUB R1 A R1
MUL R2 H K
ADD R2 G R2
DIV X R1 R2
b.
MOV R1 D
MUL R1 E
SUB R1 F
MUL R1 C
ADD R1 A
SUB R1 B
MOV R2 H
MUL R2 K
ADD R2 G
DIV R1 R2
MOV X R1
c.
LOAD D
MUL E
SUB F
MUL C
SUB B
ADD A
STORE X
LOAD H
MUL K
ADD G
DIV X
STORE X
8.13
OPCODE MODE REG ADDRESS
5 3 6 18 = 32bit.
8.14
a. Y=Z
b. M[Y]=Z
c. (W+2)+Y=Z
d. Y+X=Z
8.15. X=(-251) IN DECIMAL
b. 1111 0000 0101
c.0010 1110 1111
+ 1111 0000 0101
= 0001 1111 0100
TRUE
8-16. a. 3
b. 2
8-17. ZERO
8-18. a. 400
b. 301
c. 702
d. 200
e. 600
8-21. a. AND 1111 1111 0000 0000
b. OR 0000 0000 1111 1111
c. XOR 0000 1111 1111 0000
8-32. PC SP Top of Stack
a. 1120 3560 5320
b. 6720 3559 1122
c. 1122 3560 5320
8-33. I/O Interrupts are:
- Hardware initiated
- requires to push PSW, data of registers and PC
- address of the interrupt subroutine is generated from H/W.
TO BE CONTINUED......
:P
.^_^.
